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  1. Alexander Kushnerov
  2. Notable Answerer
  3. About Bizen
  4. Saturday, 28 December 2019
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Could I ask a number of principal and long enough questions?

1) Since Bizen transistor looks symmetric, does it bear resemblance with JFET? If yes, how it differs from the normally-off complementary JFETs presented in the patent US6307223? If no, could the logic gates built of the Bizen transistors be considered as a version of I2L, as for example US4160918?
2) What is the maximum voltage allowed at the input of Bizen transistor? Do the Zener diodes protect the inputs?
What is the maximum number of inputs the Bizen transistor can have (within the existing technology)? If this number is greater than three, could a reversible breakdown occur between the inputs? It occurs between the emmitters in TTL see P. A. Mohan et al., "Negative resistance in multiemitter transistors," Proceedings of the IEEE, 63(11), pp.1612-1613, 1975.
3) Is the Bizen technology compatible with the planar CMOS process? If yes, can it be scaled down to 28 nm?
4) Do you have a SPICE model of the Bizen transistor? For quick start even not so accurate model will be good. Which CADs allow post layout simulation of the Bizen circuits?
5) Have you compared the susceptibility of the Bizen and CMOS transistors to ionizing radiation?

Thank you,
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Hi Alex
Thank you for your interest in Bizen. See the answers to your questions below.

JFET and I2L
I can understand why you drew a comparison between the Bizen transistor and the JFET because they both allow a current flow by default, but the comparison only really goes that far. The JFET is a completely different process that is higher cost and very different characteristics.
For the second part of your question comparing I2L to Bizen, Bizen is a single transistor rather than I2L which is formed from a combination of bipolar transistors. I2L is a great logic innovation but I believe I2L has an ON/OFF base voltage swing and a current feed line which increases interconnects. It has issues with fan-out, back-feed, power consumption vs speed, integration and so cell density. Some early CPUs were made in I2L but I don't see how it's practical for a modern CPU. These are some of the reasons why it was superseded by CMOS. The Bizen transistor, however, is designed both as an alternative to the MOSFET and to supersede CMOS in a single device.

The Bizen process allows complex circuits that can have very high voltages. There is more than one type of Bizen transistors in the process, some very fast, some with power. The Zener effect inherently safely stops the issue of ESD but should not be confused with limiting high voltage inputs. You will need the PDK to put numbers on this. I understand the emitter based limitation. Multi-tunnel Bizen covered later in the patent family does not have this limitatinon because the input is isolated. This allows wide address bus decoding creating CPU logic compression (similar to cell density) to increase up above 10:1 over CMOS. The number of interconects is a major issue in CPU design. CMOS has an advantage over I2L and Bizen has an advantage over CMOS in that for a given IC, there will be a lower number of interconnects on the metal layers.

Bizen is not a CMOS process so you could not fab MOSFETS at the same time but we don’t see why you would want to. The idea is the Bizen transistor is an alternative to the MOSFET which has the benefits of Bipolar, with the disadvantages removed by quantum mechanics. We currently see no issues why it can’t be scaled down in exactly the same way CMOS was to 28nm. The projects for scaling are ongoing and not proven yet. Our main focus at the moment is power, the reasons for which will be announced soon with a very exciting press release currently under embargo.

We do have early spice models for Bizen generated from characterising devices in physical silicon. These exist in Cadence Virtuoso as part of the PDK which is growing rapidly helped by the FAB spin time. You can register interest to be an early adopter gaining time to market by using our in house designers ahead of the PDK release.

Every interface between n-doped silicon and oxide has susceptibility to total dose radiation because as the dose builds up, it causes positive charge but we believe Bizen has a fundamental advantage over CMOS and Traditional bipolar because Bizen is fundamentally Zener Mechanics and it’s known that Zener mechanics exhibit very high immunity to irradiation, including accumulated X-ray TID. Also, Bizen has no logic level PNPN or NPNP structures negating latch-up. It will still be necessary to test the specific application. We have experts in our team that can advise in these areas.

Best Regards
Bizen Support
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